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MOD Counters

MOD Counters

MOD Counters are cascaded counter circuits which count to a set modulus value before resetting

The job of a counter is to count by advancing the contents of the counter by one count with each clock pulse. Counters which advance their sequence of numbers or states when activated by a clock input are said to operate in a “count-up” mode. Likewise, counters which decrease their sequence of numbers or states when activated by a clock input are said to operate in a “count-down” mode. Counters that operate in both the UP and DOWN modes, are called bidirectional counters.

Counters are sequential logic devices that are activated or triggered by an external timing pulse or clock signal. A counter can be constructed to operate as a synchronous circuit or as an asynchronous circuit. With synchronous counters, all the data bits change synchronously with the application of a clock signal. Whereas an asynchronous counter circuit is independent of the input clock so the data bits change state at different times one after the other.

Then counters are sequential logic devices that follow a predetermined sequence of counting states which are triggered by an external clock (CLK) signal. The number of states or counting sequences through which a particular counter advances before returning once again back to its original first state is called the modulus (MOD). In other words, the modulus (or just modulo) is the number of states the counter counts and is the dividing number of the counter.

Modulus Counters, or simply MOD counters, are defined based on the number of states that the counter will sequence through before returning back to its original value. For example, a 2-bit counter that counts from 002 to 112 in binary, that is 0 to 3 in decimal, has a modulus value of 4 ( 00 → 01 → 10 → 11, and return back to 00 ) so would therefore be called a modulo-4, or mod-4, counter. Note also that it has taken four clock pulses to get from 00 to 11.

As in this simple example there are only two bits, ( n = 2 ) then the maximum number of possible output states (maximum modulus) for the counter is: 2n = 22 or 4. However, counters can be designed to count to any number of 2n states in their sequence by cascading together multiple counting stages to produce a single modulus or MOD-N counter.

Therefore, a “Mod-N” counter will require “N” number of flip-flops connected together to count a single data bit while providing 2n different output states, (n is the number of bits). Note that N is always a whole integer value.

The we can see that MOD counters have a modulus value that is an integral power of 2, that is, 2, 4, 8, 16 and so on to produce an n-bit counter depending on the number of flip-flops used, and how they are connected, determining the type and modulus of the counter.

D-type Flip-flops

MOD counters are made using “flip-flops” and a single flip-flop can produce a count of 0 or 1, giving a maximum count of 2. There are different types of flip-flop designs we could use, the S-R, the J-K, J-K Master-slave, the D-type or even the T-type flip-flop to construct a counter. But to keep things simple, we will use the D-type flip-flop, (DFF) also known as a Data Latch, because a single data input and external clock signal are used, and is also positive edge triggered.

The D-type flip-flop, such as the TTL 74LS74, can be made from either S-R or J-K based edge-triggered flip-flops depending on whether you want it to change state either on the positive or leading edge (0 to 1 transition) or on the negative or trailing edge (1 to 0 transition) of the clock pulse. Here we will assume a positive, leading-edge triggered flip-flop. You can find more information in the following link about D-type flip-flops.

D-type Flip-flop and Truth Table

d type flip flop

The operation of a D-type flip-flop, (DFF) is very simple as it only has a single data input, called “D”, and an additional clock “CLK” input. This allows a single data bit (0 or 1) to be stored under the control of the clock signal thus making the D-type flip-flop a synchronous device because the data on the inputs is transferred to the flip-flops output only on the triggering edge of the clock pulse.

So from the truth table, if there is a logic “1” (HIGH) on the Data input when a positive clock pulse is applied, the flip-flop SET’s and stores a logic “1” at “Q”, and a complimentary “0” at Q. Likewise, if there is a LOW on the Data input when another positive clock pulse is applied, the flip-flop RESET’s and stores a “0” at “Q”, and a resulting “1” at Q.

Then the output “Q” of the D-type flip-flop responds to the value of the input “D” when the clock (CLK) input is HIGH. When the clock input is LOW, the condition at “Q”, either “1” or “0” is held until the next time the clock signal goes HIGH to logic level “1”. Therefore the output at “Q” only changes state when the clock input changes from a “0” (LOW) value to a “1” (HIGH) making it a positive edge triggered D-type flip-flop. Note that negative edge-triggered flip-flops work in exactly the same way except that the falling edge of the clock pulse is the triggering edge.

So now we know how an edge-triggered D-type flip-flop works, lets look at connecting some together to form a MOD counter.

Divide-by-Two Counter

The edge-triggered D-type flip-flop is a useful and versatile building block to construct a MOD counter or any other type of sequential logic circuit. By connecting the Q output back to the “D” input as shown, and creating a feedback loop, we can convert it into a binary divide-by-two counter using the clock input only as the Q output signal is always the inverse of the Q output signal.

Divide-by-two Counter and Timing Diagram

divide by two mod counters

The timing diagrams show that the “Q” output waveform has a frequency exactly one-half that of the clock input, thus the flip-flop acts as a frequency divider. If we added another D-type flip-flop so that the output at “Q” was the input to the second DFF, then the output signal from this second DFF would be one-quarter of the clock input frequency, and so on. So for an “n” number of flip-flops, the output frequency is divided by 2n, in steps of 2.

Note that this method of frequency division is very handy for use in sequential counting circuits. For example, a 60Hz mains frequency signal could be reduced to a 1Hz timing signal by using a divide-by-60 counter. A divide-by-6 counter would divide the 60Hz down to 10Hz which is then feed to a divide-by-10 counter to divide the 10Hz down to a 1Hz timing signal or pulse, etc.

MOD-4 Counter

Technically as well as being a 1-bit storage device, a single flip-flop on its own could be thought of as a MOD-2 counter, as it has a single output resulting in a count of two, either a 0 or 1, on the application of the clock signal. But a single flip-flop on its own produces a limited counting sequence, so by connecting together more flip-flops to form a chain, we can increase the counting capacity and construct a MOD counter of any value.

If a single flip-flop can be considered as a modulo-2 or MOD-2 counter, then adding a second flip-flop would give us a MOD-4 counter allowing it to count in four discrete steps. The overall effect would be to divide the original clock input signal by four. Then the binary sequence for this 2-bit MOD-4 counter would be: 00, 01, 10, and 11 as shown.

MOD-4 Counter and Timing Diagram

mod counter

Note that for simplicity, the switching transitions of QA, QB and CLK in the above timing diagram are shown to be simultaneous even though this connection represents an asynchronous counter. In reality there would be a very small switching delay between the application of the positive going clock (CLK) signal, and the outputs at QA and QB.

We can show visually the operation of this 2-bit asynchronous counter using a truth table and state diagram.

MOD-4 Counter State Diagram

Clock Pulse Present State   Next State State Diagram
QB QA   QB QA mod counter state diagram
0 (start) 0 0 0 1
1 0 1 1 0
2 1 0 1 1
3 1 1 0 0
4 (repeat) 0 0 0 1

We can see from the truth table of the counter, and by reading the values of QA and QB, when QA = 0 and QB = 0, the count is 00. After the application of the clock pulse, the values become QA = 1, QB = 0, giving a count of 01. After the arrival of the next clock pulse, the values change and become QA = 0, QB = 1, giving a count of 10. Finally the values become QA = 1, QB = 1, giving a count of 11. The application of the next clock pulse causes the count to return back to 00, and thereafter it counts continuously up in a binary sequence of: 00, 01, 10, 11, 00, 01 …etc.

Then we have seen that a MOD-2 counter consists of a single flip-flop and a MOD-4 counter requires two flip-flops,allowing it to count in four discrete steps. We could easily add another flip-flop onto the end of a MOD-4 counter to produce a MOD-8 counter giving us a 23 binary sequence of counting from 000 up to 111, before resetting back to 000. A fourth flip-flop would make a MOD-16 counter and so on, in fact we could go on adding extra flip-flops for as long as we wanted.

MOD-8 Counter and State Diagram

mod-8 mod counters

We can therefore construct mod counters to have a natural count of 2n states giving counters with mod counts of 2, 4, 8, 16, and so on, before repeating itself. But sometimes it is necessary to have a modulus counter that resets its count back to zero during the normal counting process and does not have a modulo that is a power of 2. For example, a counter having a modulus of 3, 5, 6, or 10.

Counters of Modulo “m”

Counters, either synchronous or asynchronous progress one count at a time in a set binary progression and as a result an “n”-bit counter functions naturally as a modulo 2n counter. But we can construct mod counters to count to any value we want by using one or more external logic gates causing it to skip a few output states and terminate at any count resetting the counter back to zero, that is all flip-flops have Q = 0.

In the case of modulo “m” counters, they do not count to all their possible states, but instead count to the “m” value and then return to zero. Obviously, “m” is a number smaller than 2n, (m < 2n). So how do we get a binary counter to return to zero part way through its count.

Fortunately, as well as counting, up or down, counters can also have additional inputs called CLEAR and PRESET which makes it possible to clear the count to zero, (all Q = 0) or to preset the counter to some initial value. The TTL 74LS74 has active-low Preset and Clear inputs.

Let’s assume for simplicity that the CLEAR inputs are all connected together and are active-high inputs allowing the flip-flops to operate normally when the Clear input is equal to 0 (LOW). But if the Clear input is at logic level “1” (HIGH), then the next positive edge of the clock signal will reset all the flip-flops into the state Q = 0, regardless of the value of the next clock signal.

Note also that as all the Clear inputs are connected together, a single pulse can also be used to clear the outputs (Q) of all the flip-flops to zero before counting starts to ensure that the count actually starts from zero. Also some larger bit counters have an additional ENABLE or INHIBIT input pin which allows the counter to stop the count at any point in the counting cycle and hold its present state, before being allowed to continue counting again. This means the counter can be stopped and started at will without resetting the outputs to zero.

Modulo-5 Mod Counters

Suppose we want to design a MOD-5 counter, how could we do that. First we know that “m = 5”, so 2n must be greater than 5. As 21 = 2, 22 = 4, 23 = 8, and 8 is greater than 5, then we need a counter with at least three flip-flops (N = 3) to give us a natural binary count of 000 to 111 (0 to 7 decimal).

Using the MOD-8 counter example from above. The truth table for its natural count will be given as:

MOD-8 Counter and Truth Table

mod counters and truth table

As we want to construct a MOD-5 counter, we need to modify the above 3-bit counter circuit so that it will reset itself back to zero after a count of 5. That is a count sequence of: 1→2→3→4→5→reset, and so on.

A MOD-5 counter would produce a 3-bit binary count sequence from 0 to 4, as 000 is a valid count state, giving us a binary count sequency of: 000, 001, 010, 011, 100. Therefore we need the counter circuit to reset itself on the next counting state as the count of six (the next count) would produce an output condition of: QA = 1, QB = 0, and QC = 1 in binary as shown in the following state diagram.

MOD-5 Count Sequence

mod-5 count sequence

We can decode this output state of 101 (5) to give us a signal to clear (Clr) the counter back to zero with the help of a 3-input AND gate (TTL 74LS11) and an inverter or NOT gate, (TTL 74LS04). The inputs of the combinational logic circuit consisting of an inverter and a digital logic AND gate are connected to 3-bit counters outputs of: QA, QB, and QC respectively.

3 input and gate

The output of the 3-input AND gate will therefore be at logic level “0” (LOW) for any combinations of the inputs, other than the input sequence we want.

In binary code, the output sequence count will look like this: 000, 001, 010, 011, 100.

While it appears that the counter counts up to the 101 state, when the asynchronous count sequence reaches the next binary state of 101 (5), the combinational logic decoding circuit will detect this 101 condition, so the AND gate will produce a logic level “1” (HIGH) output resetting the counter back to its initial zero state. Thus the counter only remains in this 101 temporary state for only a few nanoseconds before it resets back to 000.

Therefore we can use the input decoding of the AND gate to reset the counter back to zero after its output of 5 (decimal) count giving us the required MOD-5 counter. When the output from the decoding circuit is LOW, it has no effect on the counting sequence.

Modulus 5 Mod Counters and Truth Table

5 mod counters circuit

Then we can use combinational logic decoding circuits around a basic counter, either synchronous or asynchronous to produce any type of MOD Counter we require as each of the counters unique output states can be decoded to reset the counter at the desired count.

In our simple MOD-5 example above, we have used a 3-input AND gate to decode the 101 binary output state, but any logic circuit can be used to reset the flip-flops at the required count.

However, one of the disadvantages of using asynchronous counters to produce any size of MOD counter of a desired count is that undesired effects called “glitches” can occur when the counter reaches its reset condition.

During this brief time the outputs of the counter may take on an incorrect value, so it is sometimes better to use synchronous counters as modulo-m counters as all the flip-flops are clocked by the same clock signal so change state at the same time.

Modulus 10 Mod Counters

A good example of a modulo-m counter circuit which uses external combinational circuits to produce a counter with a modulus of 10 is the Decade Counter. Decade (divide-by-10) counters such as the TTL 74LS90, have 10 states in its counting sequence making it suitable for human interfacing where a digital display is required.

The decade counter has four outputs producing a 4-bit binary number and by using external AND and OR gates we can detect the occurrence of the 9th counting state to reset the counter back to zero. As with other mod counters, it receives an input clock pulse, one by one, and counts up from 0 to 9 repeatedly.

Once it reaches the count 9 (1001 in binary), the counter goes back to 0000 instead of continuing on to 1010. The basic circuit of a decade counter can be made from JK flip-flops (TTL 74LS73) that switch state on the negative trailing-edge of the clock signal as shown.

MOD-10 Decade Counter

10 decade mod counters

MOD Counters Summary

We have seen in this tutorial about MOD Counters that binary counters are sequential circuits that generate binary sequences of bits as a result of a clock signal and the state of a binary counter is determined by the specific combination formed by all the counters outputs together.

The number of different output states a counter can produce is called the modulo or modulus of the counter. The Modulus (or MOD-number) of a counter is the total number of unique states it passes through in one complete counting cycle with a mod-n counter being described also as a divide-by-n counter.

The modulus of a counter is given as: 2n where n = number of flip-flops. So a 3 flip-flop counter will have a maximum count of 23 = 8 counting states and would be called a MOD-8 counter. The maximum binary number that can be counted by the counter is 2n–1 giving a maximum count of (111)2 = 23–1 = 710. Then the counter counts from 0 to 7.

Common MOD counters include those with MOD numbers of 2, 4, 8 and 16 and with the use of external combinational circuits can be configured to count to any predetermined value other than one with a maximum 2n modulus. In general, any arrangement of a “m” number of flip-flops can be used to construct any MOD counter.

A common modulus for counters with truncated sequences is ten (1010), called MOD-10. A counter with ten states in its sequence is known as a decade counter. Decade counters are useful for interfacing to digital displays. Other MOD counters include the MOD-6 or MOD-12 counter which have applications in digital clocks to display the time of day.

77 Comments

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  • Sarah

    Can anyone help me out, please? I am looking for a schematic for a circuit. A single digit 7 segment common cathode numeric display that ONLY counts from 1 – 8 then starts over.
    1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, etc.

    Please. Only show a circuit that will do the above. No zeros or nines or it won’t work.
    I’m building a musical step sequencer, an eight step, to be precise.

    • Jeremiah

      Hello Sarah,

      The easiest way to do it would be with an Arduino Nano or similar. Would that be a feasible option for you?

  • Jeremiah Gregg

    Excellent, helpful tutorial – thank you! The decoder circuit to reset the counter would only need to detect and clear the 1’s. That would save a few components.

  • Laxman Buddhewad

    Best explanation sir thank you

  • Anena Cuthbert Wanitho

    Understanding mod 5 made me to understand mod 13. Thanks.

  • เรืองยุทธ เรืองสกุล

    Thank you
    For good information.

  • Harini

    Give me some explanation of the output for modulo-16 counter

  • Paul

    Wrong!!, the information below: A counter starts from 000 to 111 is a decimal count from 0 to 8… And 0 to 8 decimal is not called a MOD-8
    Right Answer: 000 to 111 is a decimal count from 0 to 7; meaning for simplicity is that there 8 items to be count such as: 0,1,2,3,4,5,6,7 which implies MOD-8 counter.
    And 0 to 8 decimal count is a MOD-9 counter, not a MOD-8…

  • Nyiramahirwe Sandrine

    Don’t understand the modulus and modulo.

    • Wayne Storr

      A counters “Modulus” value is the number of switching states that the counter must sequence through before returning back to its original value. For example, a counter that counts upwards from 0002 to 1112 in binary (or 0 to 7 in decimal) will have a modulus of 8 and would therefore be called a Modulo-8, or Mod-8, counter. The maximum number of output states, and therefore the maximum modulus of a counter, would be 2n where “n” is the number of output states.

  • Mansa

    Modulus 200

  • Godwin Shonga

    oh! this subject is very useful to me and from now on i will be able to light the leds.
    thanks

  • Giannis

    What changes if we want to start the modulus counter from a particular number. For example a mod 16 counter from 1010 to 1111

    • Paul

      If you want to build the counter to start from 1010 to 1111… it’s called a mod-6 counter. The count starts from 10,11,12,13,14,15 in the decimal system. Notice 6 states, which refers to either mod6 or divide6 counter.

      * You can checkout 74LS193 presettable 4-bit synchronous u/d counter.
      there are 4 data pins to load data(parallel load)… the parallel load pin(PL) has to be
      low to carry out input data(d3,d2,d1,d0) to the Q outputs(q3,q2,q1,q0). So you want to load 1010 initially.
      You have to understand the truth table to this chip… referred to the datasheet.
      The parallel load pin has to be low for short period then goes back to high logic to
      preload your data(1010)… you can use simple series RC circuit perform such task.
      Capacitor slowly charge a low voltage then goes high base on the RC time constant.

      Secondly, if the count needs to start at 10 to 15 and recycle over time. when count gets to 1111(15) you need to logically preload the data(1010) after again. The trick
      is 1111 is distinct in the count; so you count use a 4-bit NAND gate and have the nand gate output controls the PL(load pin). 1111 on a 4bit nand gate inputs to gives a low on the output.

      Regardless the set-up is pretty tricky… you have to play with it and get familiarize by experimenting. Study the truth table, and RC and RL(series circuit) are handy in digital design… being that they are transient( low or high for a short period)… so base on after the preload of the data 1010 after the last count 1111 – you may have to strobe the parallel load(PL)pin for a short period.

  • Shifa Mobin

    Nice explanation!

    • Paul

      Thanks a lot for the positive comment, l think it is just a typo on the website info posting… Can be terrible though!
      * The more l even look back on his material, it seem to be a MOD-6 counter and not a MOD-5.
      l notice his diagram: As soon as the counter gets to 110(decimal 6) it resets to 000.
      So you have: 000, 001,010,011,100,101 in a continuous recycling pattern. There are six(6) elements in which l have shown. And that is the reason why it is called a Divide by 6 counter; 6 divisional parts.
      So it is a MOD-6 counter.

  • Sakshi phopase

    Hello

  • Paul

    In your example MOD-5 counter and truth table, l am not sure about it, shouldn’t the waveforms be for a MOD-7 counter instead? A MOD-5 counter has 5 states which count from 0000 to 0100, decimal 0 to 4 count… Not sure what the explanation was actually intended for?
    l notice the counter start from Count(0000) to (0110) – 7 states… obviously, l am using 4 bits instead of 3 bits, it’s fine though. A decimal count 2 thru 6 would be a MOD-5.

  • Ronald Too

    Please send mode 16

  • Renato Lopez

    If you can’t receive an answer within 30 minutes then just comment below.

  • Vamshi Krishna

    I have a small ambiguiuty regarding the clk inputs given for the flipflops in the counters. For example take the Mod 4 counter and its timing diagram mentioined above. Qa is getting triggered whenever there is a rising edge in the clock, which is fine. When we come to Qb, from the timing diagram we see that, it should get triggered when ever there is a falling transition in Qa. So shouldn’t we give Qa_bar as the clk input for DFF2?

  • Naseem shoukat

    plz send the material of mod 9 and 11 counter

  • Zunaira Munir

    How to made a 2 bit 4 Mod synchronous up/down random counter using series 1,3,5,2

  • Solana

    How do you write the logical condition to truncate a mod 9 counter?