The JK Flip-Flop
From the previous tutorial we now know that the basic gated SR NAND Flip-flop suffers from
two basic problems: Number 1, the S = 0 and R = 0
condition or S = R = 0 must always be avoided,
and number 2, if S or R change state while the enable input is high the
correct latching action will not occur. Then to overcome these two problems the JK Flip-Flop was developed.
The JK Flip-Flop is basically a Gated SR Flip-Flop with the addition of clock input
circuitry that prevents the illegal or invalid output that can occur when both input S equals
logic level "1" and input R equals logic level "1". The symbol for a JK Flip-flop is similar
to that of an SR Bistable as seen in the previous tutorial except for
the addition of a clock input.
The JK Flip-flop
Both the S and the R inputs of the previous SR
bistable have now been replaced by two inputs called the J and K
inputs, respectively. The two 2-input NAND gates of the gated SR bistable have now been replaced
by two 3-input AND gates with the third input of each gate connected to the outputs
Q and Q. This cross coupling of the SR Flip-flop allows the previously
invalid condition of S = "1" and R = "1" state to be usefully used
to turn it into a "Toggle action" as the two inputs are now interlocked. If the circuit is "Set" the
J input is inhibited by the "0" status of the Q through the lower
AND gate. If the circuit is "Reset" the K input is inhibited
by the "0" status of Q through the upper AND gate. When both inputs
J and K are equal to logic "1", the JK flip-flop changes state and the
truth table for this is given below.
The Truth Table for the JK Function
| J | K | Q |
Q | same as
for the
SR Latch |
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | toggle
action |
| 1 | 1 | 1 | 0 |
Then the JK Flip-flop is basically an SR Flip-flop with feedback and which enables only one of its
two input terminals, either Set or Reset at any one time thereby eliminating the invalid condition seen previously in
the SR Flip-flop circuit. Also when both the J and the K inputs are
at logic level "1" at the same time, and the clock input is pulsed either "HIGH" or "LOW" the circuit will "Toggle"
from a Set state to a Reset state, or visa-versa. This results in the JK Flip-flop acting more like a
T-type Flip-flop when both terminals are "HIGH".
Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called "race" if the output Q changes state before the timing pulse of the clock input
has time to go "OFF". To avoid this the timing pulse period (T) must be kept as short as possible
(high frequency). As this is sometimes is not possible with modern TTL IC's the much improved Master-Slave JK Flip-flop
was developed. This eliminates all the timing problems by using two SR flip-flops connected together in series, one for the
"Master" circuit, which triggers on the leading edge of the clock pulse and the other, the "Slave" circuit, which triggers
on the falling edge of the clock pulse.
Master-Slave JK Flip-flop
The Master-Slave Flip-Flop is basically two JK bistable flip-flops connected together
in a series configuration with the outputs from Q and Q from the "Slave"
flip-flop being fed back to the inputs of the "Master" with the outputs of the "Master" flip-flop being connected to
the two inputs of the "Slave" flip-flop as shown below.
Master-Slave JK Flip-Flops
The input signals J and K are connected to the
"Master" flip-flop which "locks" the input while the clock (Clk) input is high at logic
level "1". As the clock input of the "Slave" flip-flop is the inverse (complement) of the "Master" clock input, the
outputs from the "Master" flip-flop are only "seen" by the "Slave" flip-flop when the clock input goes "LOW" to logic
level "0". Therefore on the "High-to-Low" transition of the clock pulse the locked outputs of the "Master" flip-flop
are fed through to the JK inputs of the "Slave" flip-flop making this type of flip-flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the
output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a
"Synchronous" device as it only passes data with the timing of the clock signal.
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